A

• [+] ARM architecture (0)
• [+] Advanced RISC Computing (0)

B

• [+] Backward compatibility (1)

C

• [+] Central processing unit (2)
• [+] Classes of computers (22)

C cont.

• [+] Computer arithmetic (3)
• [+] Consistency model (0)

F

• [+] Flynn's Taxonomy (0)

I

• [+] Instruction processing (1)
• [+] Interrupts (0)

N

• [+] Network architecture (8)

O

• [+] Operating system kernels (5)
• [+] Operating systems by architecture (3)

P

• [+] Power Architecture (6)

R

• [+] Computer hardware researchers (0)

X

• [+] X86 architecture (6)

• Computer architecture

A

• AVR32 architecture
• Abstraction layer
• Address space
• Addressing mode
• Anti machine
• Application-specific instruction-set processor

B

• Bridging model
• Burroughs large systems descriptors
• Burton Smith

C

• Central Processor Unit

D

• Dataflow
• Dataflow architecture
• Datapath
• Dynamic voltage scaling

E

• EISC
• Esção
• Explicit Data Graph Execution

F

• Fault-tolerant computer systems

F cont.

• Flexible Architecture for Simulation and Testing
• Frequency scaling

H

• Hardware architect
• Harvard architecture

I

• IEEE Transactions on Computers
• IOMMU
• Intel Tera-Scale
• Interconnect processing unit

K

• Killer NIC

L

• Logic family

M

• MIC-1
• MIPS architecture
• MSPA
• Microarchitecture
• Modified Harvard architecture
• Multi-core

N

• NonStop

O

• OpenRISC 1200

P

• PipeRench
• Popek and Goldberg virtualization requirements

P cont.

• Processor book
• Processor-in-memory

R

• Reference model
• Remote Graphics Unit (RGU)

S

• Simultaneous multithreading
• Single Point of Failure
• Slot (computer architecture)
• Stanford Smart Memories Project
• Stream processing
• Super harvard
• Superscalar
• System bus model

T

• Transport triggered architecture

U

• Unicore

V

• Vaakya Architecture
• Von Neumann architecture
• Von Neumann syndrome

Z

• Zero address arithmetic