A

• [+] ARM architecture (27 P)
• [+] Advanced RISC Computing (13 P)

C

• [+] Central processing unit (3 C, 70 P)
• [+] Classes of computers (20 C, 73 P)
• [+] Computer arithmetic (2 C, 129 P)
• [+] Consistency model (13 P)

D

• [+] Distributed computing architecture (16 C, 62 P)

F

• [+] Flynn's Taxonomy (12 P)

I

• [+] Instruction processing (2 C, 66 P)
• [+] Instruction set architectures (29 P)
• [+] Interoperability (2 C, 37 P)
• [+] Interrupts (31 P)

N

• [+] Network architecture (8 C, 111 P)

O

• [+] Operating system kernels (5 C, 26 P)
• [+] Operating systems by architecture (3 C)

P

• [+] Power Architecture (7 C, 85 P)

R

• [+] Computer hardware researchers (5 P)

X

• [+] X86 architecture (6 C, 52 P)

• Computer architecture

A

• Abstraction layer
• Address space
• Addressing mode

B

• Bridging model
• Burroughs large systems descriptors

C

• Cellular architecture
• Comparison of CPU architectures
• Computer architecture simulator
• Cross-Platform Support Middleware

D

• Dataflow
• Dataflow architecture

E

• Embryonics Project
• Explicit Data Graph Execution
• Extendable instruction set computer

F

• Fault-tolerant computer systems
• Flexible Architecture for Simulation and Testing
• Fraglets
• Frequency scaling

H

• Hardware architect
• Harvard architecture
• Heterogeneous computing
• Hybrid-core computing

I

• IEEE Transactions on Computers
• IOMMU
• Intel Tera-Scale
• Interconnect processing unit
• International Symposium on Computer Architecture

M

• MIC-1
• Memory ordering
• Microarchitecture
• Modified Harvard architecture
• Multi-core processor
• Multiprogramming

N

• NEC SX architecture
• Ne-XVP
• Network Centric Product Support
• NonStop

O

• Open architecture

P

• Popek and Goldberg virtualization requirements
• Processor-in-memory

R

• Reference model
• User:Rpmasson/hybrid-core

S

• Semantic service oriented architecture
• Simultaneous multithreading
• Single point of failure
• Single core architecture
• Slot (computer architecture)
• Stream processing
• Superscalar
• System bus model

T

• Tagged architecture

V

• Vaakya Architecture
• Von Neumann architecture
• Von Neumann syndrome

Z

• Zero address arithmetic