A

• [+] ARM architecture (0)
• [+] Advanced RISC Computing (0)

C

• [+] Central processing unit (3)
• [+] Classes of computers (17)
• [+] Computer arithmetic (2)

C cont.

• [+] Consistency model (0)

F

• [+] Flynn's Taxonomy (0)

I

• [+] Instruction processing (2)
• [+] Interoperability (2)
• [+] Interrupts (0)

N

• [+] Network architecture (8)

O

• [+] Operating system kernels (5)
• [+] Operating systems by architecture (3)

P

• [+] Power Architecture (7)

R

• [+] Computer hardware researchers (0)

X

• [+] X86 architecture (6)

• Computer architecture

A

• Abstraction layer
• Address space
• Addressing mode

B

• Bridging model
• Burroughs large systems descriptors

C

• Cellular architecture
• Comparison of CPU architectures
• Computer architecture simulator
• Cross-Platform Support Middleware

D

• Dataflow
• Dataflow architecture

E

• Embryonics Project
• Esção
• Explicit Data Graph Execution
• Extendable instruction set computer

F

• Fault-tolerant computer systems

F cont.

• Flexible Architecture for Simulation and Testing
• Fraglets
• Frequency scaling

H

• Hardware architect
• Harvard architecture
• HyperText Computer

I

• IEEE Transactions on Computers
• IOMMU
• Intel Tera-Scale
• Interconnect processing unit
• International Symposium on Computer Architecture

M

• MIC-1
• MIPS architecture
• MSPA
• Microarchitecture
• Modified Harvard architecture
• Multi-core

N

• NonStop

O

• Open architecture
• OpenRISC 1200

P

• Popek and Goldberg virtualization requirements
• Processor-in-memory

R

• Reference model

S

• Semantic service oriented architecture
• Simultaneous multithreading
• Single Point of Failure
• Slot (computer architecture)
• Stream processing
• Superscalar
• System bus model

T

• Tagged architecture

V

• Vaakya Architecture
• Von Neumann architecture
• Von Neumann syndrome

Z

• Zero address arithmetic